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| European Case Law Identifier: | ECLI:EP:BA:2003:T018800.20030505 | ||||||||
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| Date of decision: | 05 May 2003 | ||||||||
| Case number: | T 0188/00 | ||||||||
| Application number: | 91104125.9 | ||||||||
| IPC class: | H01L 21/48 | ||||||||
| Language of proceedings: | EN | ||||||||
| Distribution: | B | ||||||||
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| Title of application: | Multilayer interconnection structure | ||||||||
| Applicant name: | FUJITSU LIMITED | ||||||||
| Opponent name: | – | ||||||||
| Board: | 3.4.03 | ||||||||
| Headnote: | – | ||||||||
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| Keywords: | Inventive step (yes) Prior art documents which relate to different devices – no incentive to combine Refund of further search fee (yes) – review by the examining division of the finding of lack of unity based on a document not cited in the partial search report |
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Summary of Facts and Submissions
I. European patent application No. 91 104 125.9 was refused in a decision of the examining division dated 28. September 1999. The ground for the refusal was that the application did not meet the requirements of novelty and inventive step having regard to the prior art documents
D1: Proceedings of the Sixth International Electronic Manufacturing Technology Symposium IEMT, Nara (JP), 26 to 28 April 1989, pages 128 to 131;
D4: US-A-4 917 759;
D5: EP-A-0 329 969; and
D6: EP-A-0 324 198.
It was also held in the decision that the application did not meet the requirement of unity of invention.
Furthermore, a request for a refund of an additional search fee was rejected.
II. Claim 1 according to the main request under consideration in the decision under appeal reads as follows, where the amendments with respect to claim 1 as filed have been highlighted by the Board:
“1. A method of fabricating a multilayer structure, comprising:-
(a) forming a first electrically conductive layering (2, 3);
(b) providing a resist layer (4) with a via hole (4A), said via hole being located on said first electrically conductive layering;
(c) forming a via lead (5) in said via hole by electrically plating a metal therein;
(d) removing said resist layer (4);
(e) forming an insulative layer (7-1) of non-photosensitive material over said first electrically conductive layering (2, 3) and said via lead (5);
(f) etching a surface part of said insulative layer (7-1) until a top part of said via lead (5) protrudes by a predetermined height from the etched surface of said insulative layer; and
(g) forming a second electrically conductive layering (8; 8, 9) over said insulative layer (7-1) and over the protruding part of said via lead (5).”
III. The reasoning given in the decision under appeal, relevant to the present appeal, can be summarized as follows:
(a) Document D1 is considered to represent the closest prior art. The method of claim 1 differs from the method of document D1, Figure 1 in that
(i) the deposited insulative layer is non-photosensitive and is thinned by etching rather than by a photolithographic process; and
(ii) the via lead protrudes from the surface of the thinned insulative layer.
(b) Feature (i) avoids cumbersome thinning of the insulating layer by photolithographic means. Since document D1 mentions that polishing is not an advantageous method for thinning the insulating layer (cf. D1, “Introduction”), the skilled person would consider the relatively simple etch technique as disclosed in document D4 to be a suitable alternative.
(c) As to feature (ii), document D4 also discloses that the conductive pillar protrudes above the insulating layer. It is immediately clear and obvious for the skilled person that the protrusion has the advantage of establishing a reliable electrical contact. Therefore, the skilled person would arrive at the subject matter of claim 1 in an obvious manner.
(d) Additionally, a similar reasoning of lack of inventive step in respect of claim 1 according to the main request would apply having regard to documents D1 and D5 or documents D1 and D6.
(e) As the subject matter of claim 1 according to the main request does not involve an inventive step, the application according to the main request and first and second auxiliary requests lacks unity of invention a posteriori.
(f) The request for a refund of the additional search fee paid under Rule 46(1) EPC is refused for the following reasons:
Claim 1 as filed does not specify that the insulative layer 7-1 is made of a non-photosensitive material, and is thus broader than claim 1 according to the main request. Therefore, claim 1 as filed does not involve an inventive step for the same reasons as given above for the main request.
Furthermore, the common subject matters between dependent claims 2 and 3, claims 2 and 4, and claims 3 and 4 as filed, respectively, which all directly refer to claim 1, are known from document D1 or are considered trivial. Since dependent claims 2, 3, and 4 relate to different technical problems, the application as originally filed comprised the following separate inventions which are not so linked as to form a single general inventive concept:
1. The subject matter of claims 1, 2 and 5 to 50, and corresponding description;
2. The subject matter of claims 1, 3 and 5 to 50, and corresponding description;
3. The subject matter of claims 1, 4 and 5 to 50, and corresponding description.
The search division had in its communication under Rule 46(1) EPC indicated that the application as filed comprised two groups of inventions which correspond to the above group 1 and a combination of the above groups 2 and 3. Thus, the opinion of the search division that the application lacked unity was correct (although the second group of inventions cited by the search division actually comprised two non-unitary groups of inventions), and the demand for the payment of a further search fee was justified.
IV. The appellant (applicant) lodged an appeal on 29. November 1999, paying the appeal fee on 1 December 1999. A statement of the grounds of appeal was filed on 7. February 2000 together with new claims.
V. In response to a communication of the Board and a telephone consultation with the rapporteur of the Board, the appellant filed amended application documents with the letters dated 3 March 2003 and 17. March 2003.
VI. The appellant requested that the decision under appeal be set aside and a patent be granted on the basis of one of the following requests:
Main request:
Claims: 1 to 12 according to the main request filed with the letter dated 3 March 2003;
Description: pages 4 to 9 as originally filed,
pages 1, 2, 2a, 2b, 3 filed with the letter dated 17 March 2003;
Drawings: sheets 1/3 to 3/3 as originally filed.
First auxiliary request:
Claims: 1 to 12 according to the first auxiliary request filed with the letter dated 3. March 2003;
Description and Drawings as for the main request.
Second auxiliary request:
Claims: 1 to 9 according to the second auxiliary request filed with the statement of the grounds of appeal;
Description and Drawings as for the main request.
The appellant furthermore requested a refund of the additional search fee paid by the appellant. Oral proceedings were requested as a precaution against an adverse decision of the Board.
VII. Claim 1 according to the main request is identical in wording to claim 1 according to the main request under consideration in the decision under appeal. Claims 2 to 12 are dependent claims.
VIII. The arguments of the appellant in support of the above requests can be summarized as follows:
(a) Document D1, as the application in suit, relates to a “negative hole” method, i.e. a method where a via hole is first formed, followed by the step of depositing metal to fill the via hole. In contrast to the claimed method, however, document D1 provides a clear teaching to use a photosensitive resin as insulating layer in order to obtain a flat layer.
(b) Document D4 was published after the priority date claimed for the present invention. Contrary to the view of the examining division, claim 1 is entitled to the claimed priority date. Notwithstanding the above, document D4 relates to wiring layers in an integrated circuit chip having a feature size less than a micrometer, whereas that of document D1 is for a ceramic substrate board. The consequence is an enormous difference in feature sizes between the device disclosed in document D1 and that of document D4 (submicrometer in document D4, column 1, lines 54, 55, column 4, line 30; 30 to 130 micrometer in document D1, abstract). There is also no hint that the technique of document D4 would be either economic or practical outside the context of sub-micrometer structures.
Similarly, documents D5 and D6 also relate to submicrometer structures.
(c) Regarding the decision to refuse a refund the additional search fee, document D4 which was used in the consideration of inventive step and unity of invention by the examining division was not cited in the search report. A demand for a further search fee based on an a posteriori objection cannot be justified on the basis of a prior art document which was not cited by the search division.
Reasons for the Decision
1. The appeal complies with Articles 106 and 108 and Rule 64 EPC and is therefore admissible. The appeal is also allowable for the reasons given below.
2. Inventive step – Main Request
2.1. Document D1 was considered the closest prior art in the decision under appeal, and it discloses a method of forming a multilayer structure for a substrate package where a resist layer having a via hole is formed on a first electrically conductive layer (cf. Figure 1, “New Process”, steps (1) and (2)). A via lead is formed by electroplating metal in the via hole, and the resist layer is removed (cf. Figure 1, step (3)). A photosensitive polyimide precursor is deposited over the structure. The polyimide precursor is exposed using a mask having an exposure pattern chosen in such a manner that a flat upper surface of the insulating polyimide layer results after developing and curing (step (5)). A second conductive layer is formed over the insulative layer and the via lead (step (6)).
According to the decision under appeal, Figures 3 and 6 of document D1 do not disclose a protruding via lead. It would appear that this finding was probably due to the poor quality of reproduction of the photographs of Figures 3 and 6 in the copy of document D1 available to the examining division (cf. item III(a) above).
The Board has consulted an improved photocopy of document D1, wherein the photographs of Figures 3 and 6 of the multilayer structure clearly show that the upper surface of the via lead is convex at the stage where the photoresist has been removed, and that the via lead protrudes slightly over the surface of the insulating polyimide layer, after the insulating polyimide has been planarized. This finding has not been disputed by the appellant.
2.2. The method of claim 1 according to the main request differs from that of document D1 in that (i) a non-photosensitive material is deposited for the insulative layer, whereas in document D1, a photosensitive polyimide precursor is used; and (ii) a surface part of the insulative layer is etched to expose the top part of the via lead, whereas in document D1, a corresponding thinning of the polyimide layer is carried out by developing and curing the exposed, photosensitive polyimide layer.
The problem addressed by the application in suit thus relates to finding an alternative to the photolithographic process of document D1 for planarizing the insulating layer.
2.3. Document D4 was published on 17 April 1990 which is after the priority date 19 March 1990 claimed for the present application. It discloses a method of forming a via structure in an integrated circuit comprising the steps of depositing a layer of aluminum 20 which is patterned and etched to form a via lead 21 (cf. Figures 3 and 4), followed by the steps of depositing and etching back an interlayer oxide layer 24 so that the via lead 21 protrudes over the surface of the dielectric layer 24 (cf. Figure 5). A second conductive layer 26 is formed on the interlayer oxide layer 24 covering the via lead 21 (cf. Figure 6).
2.4. Document D5 discloses a method of forming multilayer wiring structure in an integrated circuit where via leads are formed by the steps of depositing a metal layer 28 which is etched to form via leads 20 (cf. Figures 1, 3 and 4). An interlayer insulating layer 34 is deposited on the structure and is etched back using reactive ion etching until the via leads 20 protrude above the interlayer insulating layer (cf. Figure 6; column 7, lines 27 to 38).
2.5. Thus, the method of claim 1 differs from those of documents D4 and D5 in particular in that the via lead is formed by electroplating a metal layer in an opening of a resist layer, whereas in the methods of documents D4 and D5, a blanket deposited metal layer is etched back to the shape of a via lead.
2.6. Document D6 discloses tungsten pillars formed by blanket CVD deposition of tungsten 4 filling via holes 2 in an insulating layer 1 formed on an integrated circuit (cf. Figure 2). After etch-back of the tungsten layer (cf. Figure 3), a planarization layer 7 is deposited and etched back (cf. Figure 4), so that the tungsten via leads 4A, 4B are at least planar with the insulating layer 1 (cf. Figure 5; column 10, lines 10 to 17).
The method of document D6 does not disclose a step of forming the via lead is formed by electroplating a metal layer in an opening of a resist layer, as specified in the method of claim 1.
2.7. In the decision under appeal, it was held that since document D1 discloses that thinning the insulating layer by mechanical polishing is not advantageous, the skilled person would therefore consider the relatively simple etch-back technique as disclosed in document D4 (cf. item III(b) above).
2.8. As the appellant convincingly argued, however, document D1 and the application in suit both relate to multilayer structures for e.g. hybrid integrated circuits. Such structures have feature sizes which are on the order of several tens of micrometers (cf. application as published, column 2, line 58 to column 3, line 4 disclosing a via hole having a diameter of 80 µm; D1, page 130, section (3), first and second paragraphs, disclosing via holes having diameters between 30 and 130 µm). Documents D4 to D6 on the other hand, all relate to multilayer structures of integrated circuits having a feature size less than one micrometer (cf. D4, column 1, lines 53 to 60; D5, column 2, lines 19 to 28; D6, column 1, lines 1 to 7). Furthermore, there is no hint in these documents that the planarization etch-back process disclosed in the documents D4 to D6 would be economical for layers which are at least ten times thicker.
2.9. Therefore, in the Board’s opinion, the skilled person faced with the task of improving the process of document D1 would not have any incentive to consult any of the documents D4 to D6, since they relate to processes of forming different devices from that of document D1.
2.10. In the decision under appeal, it was held that the priority date of 19 march 1990 was not validly claimed, and therefore, document D4 belonged to the state of the art as defined in Article 54(2) EPC. Since however document D4 is not relevant for the assessment of novelty and inventive step for the reasons given above, the Board sees no reason for investigating whether the above priority date is validly claimed or not.
3. Unity of invention
In the decision under appeal it was held that the application lacked unity of invention (cf. item III(d) above). Since however the subject matter of claim 1, which is the only independent claim, has been found to be novel and involve an inventive step, the application in suit necessarily meets the requirement of unity of invention as defined in Article 82 and Rule 30 EPC.
4. Refund of a further search fee
4.1. The appellant has requested a refund of the further search fee paid in response to a communication under Rule 46(1) EPC of the search division. The request for refund was rejected by the examining division which held that the subject matter of claim 1 as filed did not involve an inventive step for the same reasons as claim 1 which was refused having regard to the prior art documents D1 and D4.
4.2. The appellant argued that document D4 which was used in the inventive step objection underlying the non-unity objection was not cited in the search report, but was introduced by the examining division in its the communication accompanying summons for oral proceedings. A demand for a further search fee was therefore based on an a posteriori objection on the basis of a prior art document which was only cited long after the lack of unity objection was raised by the search division.
4.3. Rule 46(1) EPC states that if the search division considers that the application does not comply with the requirement of unity of invention, it shall draw up a partial search report on those part of the first invention mentioned in the claims. The partial search report supplemented with a specification of the separate inventions are issued with a communication informing the applicant that if the search report is to cover the other invention(s), further search fee(s) is/are to be paid within a prescribed time limit.
4.4. Under Rule 46(2) EPC, any further search fee which has been paid under Rule 46(1) EPC shall be refunded if, during the examination of the European patent application by the examining division, the applicant requests a refund and the examining division finds that the communication referred to in Rule 46(1) EPC was not justified.
4.5. It follows from the above that the examining division has to review the finding of the search division that the claims as filed lacked unity of invention. In other words, a review of the finding of lack of unity of invention has to be carried out having regard only to the facts presented by the search division in its communication under Rule 46(1) EPC. Since in most cases objections against lack of unity of invention are raised having regard to the prior art, so-called a posteriori unity objections, this means that the examining division has to base its review solely on the documents cited in the partial search report and on the specification of the different inventions drawn up by the search division, while taking into account arguments which the applicant may have submitted in support of his request for a refund.
It should also be mentioned that in the analogous procedure under the PCT, a review of the justification for the invitation to pay additional fees resulting from a finding of lack of unity is provided for in Rule 40.2(c) and (e) and Rule 68.3(c) and (e) PCT, the so-called protest procedure. The Boards of Appeal have ruled that these reviews have to be based exclusively on the reasons given in the invitation to pay having regard to the facts and arguments submitted by the applicants (cf. W 4/93, OJ EPO 1994, 939, reasons 2.1 and 2.2).
4.6. In the present case, however, the examining division reasoned that the claims as filed lacked unity of invention a posteriori, as a consequence of the finding that claim 1 as filed lacked an inventive step having regard to documents D1 and D4, where the latter document was not cited in the partial search report.
Thus, the examining division did not review the finding of lack of unity of invention within the meaning of Rule 46(2) EPC, but carried out a fresh examination on the basis of a new document D4. Therefore, the decision to refuse the refund of a further search fee has to be set aside for formal reasons alone.
For the above reasons, therefore, the appellant’s request for a refund of a further search fee under Rule 46(2) EPC is justified.
ORDER
For these reasons it is decided that:
1. The decision under appeal is set aside.
2. The case is remitted to the department of the first instance with the order to grant a patent on the basis of the documents according to the main request as specified under item VI above.
3. The refund of one further search fee is ordered.